![]() ![]() Then, with an input voltage at “A” HIGH, the output at “Q” will be LOW and an input voltage at “A” LOW the resulting output voltage at “Q” is HIGH producing the complement or inversion of the input signal. Likewise, when the transistors base input at “A” is low (0v), the transistor now switches “OFF” and no collector current flows through the resistor resulting in an output voltage at “Q” high at a value near to +Vcc. ![]() Signal Inversion using Active-low Input Bubbleīubble Notation for Input Inversion NAND and NOR Gate EquivalentsĪn Inverter or logic NOT gate can also be made using standard NAND and NOR gates by connecting together ALL their inputs to a common input signal for example. The easiest way is to think of the bubble as simply an inverter. This inversion of the input signal is not restricted to the NOT gate only but can be used on any digital circuit or gate as shown with the operation of inversion being exactly the same whether on the input or output terminal. But this bubble can also be present at the gates input to indicate an active-LOW input. The “bubble” ( o) present at the end of the NOT gate symbol above denotes a signal inversion (complementation) of the output signal. Commercial available NOT gates IC’s are available in either 4 or 6 individual gates within a single IC package. As they are single input devices, logic NOT gates are not normally classed as “decision” making devices or even as a gate, such as the AND or OR gates which have two or more logic inputs. Likewise, when their input signal is “LOW” their output state will NOT be “LOW”. Logic NOT gates provide the complement of their input signal and are so called because when their input signal is “HIGH” their output state will NOT be “HIGH”. ![]()
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